Efficient FPGA Implementation of Equalizer for Finite IntervalConstant Modulus Algorithm

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F06%3A03121413" target="_blank" >RIV/68407700:21230/06:03121413 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Efficient FPGA Implementation of Equalizer for Finite IntervalConstant Modulus Algorithm

Original language description

This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm, proposed for 4G communication systems. We used two pipelined arithmetic libraries based on the logarithmic number system or the floating-point number system, using the widely known IEEE format forthe floating-point calculations required in the algorithm. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology,which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities.

Czech name

Není k dispozici

Czech description

Není k dispozici

Type

A - Audiovisual production

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/1M0567" target="_blank" >1M0567: Centre for Applied Cybernetics</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2006

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

ISBN

1-4244-0777-X

Place of publication

Lyon

Publisher/client name

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Version

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Carrier ID

neuvedeno