Design and Debugging of Parallel Architectures Using the ISAC Language
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89659" target="_blank" >RIV/00216305:26230/10:PU89659 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Design and Debugging of Parallel Architectures Using the ISAC Language
Original language description
Trend of nowadays embedded systems is placing more than one application-specific instruction set processor (ASIP) on one chip (multi-processor systems on a chip). This allows parallel processing of multimedia and network applications, where input is usually a data stream. Each of these processors is highly optimized for a specific task. Other forms of suitable parallel architectures are very long instruction word processors (VLIW) and multi-core processors. These parallel architectures are often used inmulti-processor systems on a chip.<br><br>Architecture description languages (ADL) are very effective for <br>description of simple processors. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in these languages. Therefore, <br>we introduce new constructions of an architecture description language ISAC allowing easy and fast prototyping of such processors and systems.<br>
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings ot the Annual International Conference on Advanced Distributed and Parallel Computing and Real-Time and Embedded Systems
ISBN
978-981-08-7656-2
ISSN
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e-ISSN
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Number of pages
372
Pages from-to
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Publisher name
Global Science & Technology Forum
Place of publication
Singapore
Event location
Singapore
Event date
Nov 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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