On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96050" target="_blank" >RIV/00216305:26230/11:PU96050 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits
Original language description
Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models - compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design - giving a designer an immediate information about the change impact to testability parameters. Under the assumption, following requirements are posed to the analysis: low computational complexity and accuracy. The latter requirement is met if strong correlation is
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011
ISBN
978-0-7695-4494-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
367-374
Publisher name
IEEE Computer Society
Place of publication
Oulu
Event location
Oulu
Event date
Aug 31, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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