Implementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU101779" target="_blank" >RIV/00216305:26230/12:PU101779 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/FPL.2012.6339376" target="_blank" >http://dx.doi.org/10.1109/FPL.2012.6339376</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/FPL.2012.6339376" target="_blank" >10.1109/FPL.2012.6339376</a>
Alternative languages
Result language
angličtina
Original language name
Implementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration
Original language description
Adaptive hardware requires some reconfiguration capabilities. FPGAs with native dynamic partial reconfiguration (DPR) support pose a dilemma for system designers: whether to use native DPR or to build a virtual reconfigurable circuit (VRC) on top of theFPGA which allows selecting alternative functions by a multiplexing scheme. This solution allows much faster reconfiguration, but with higher resource overhead. This paper discusses the advantages of both implementations for a 2D image processing matrix.Results show how higher operating frequency is obtained for the matrix using DPR. However, this is compensated in the VRC during evolution due to the comparatively negligible reconfiguration time. Regarding area, the DPR implementation consumes slightlymore resources due to the reconfiguration engine, but adds further more capabilities to the system.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/ED1.1.00%2F02.0070" target="_blank" >ED1.1.00/02.0070: IT4Innovations Centre of Excellence</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proc. of the 22nd International Conference on Field Programmable Logic and Applications (FPL)
ISBN
978-1-4673-2257-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
547-550
Publisher name
IEEE Computer Society
Place of publication
Oslo
Event location
Oslo
Event date
Aug 29, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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