NAND/NOR Gate Polymorphism in Low Temperature Environment
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F12%3APU98219" target="_blank" >RIV/00216305:26230/12:PU98219 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
NAND/NOR Gate Polymorphism in Low Temperature Environment
Original language description
The fundamental aspect behind this paper is focused on behaviour of polymorphic digital circuits in potentially harsh operating environment. Unlike conventional CMOS-based circuits, the area of polymorphic electronics takes and an advantage of inherentlybuilt-in features that open up the possibility for on-the-fly adjustment of a particular circuit function with respect to the surrounding environment. The most prevalent benefit here is connected with the fact that space-efficient circuit implementationcan be achieved due to the adoption of polymorphic principles and, thus, eliminate the need for an additional function change controller. From a conceptual point of view, key attention is given to a set of experiments which were conducted with the aim to evaluate the influence of wide temperature range (with special interest in low temperatures domain) in case of reconfigurable chip with dedicated polymorphic gates. The experimental setup was based around reconfigurable polymorphic chip
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
ISBN
978-1-4673-1185-4
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
34-37
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Tallinn
Event location
Tallinn
Event date
Apr 18, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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