On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106278" target="_blank" >RIV/00216305:26230/13:PU106278 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=10235" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=10235</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2013.6549783" target="_blank" >10.1109/DDECS.2013.6549783</a>

Result language
angličtina
Original language name
On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems
Original language description
The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to preprocess all interrupts before they arrive to the system. The hardware is ready to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4673-6133-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
24-29
Publisher name
IEEE Computer Society
Place of publication
Brno
Event location
Karlovy Vary
Event date
Apr 8, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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