Memory Efficient IP Lookup in 100 Gbps Networks

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106281" target="_blank" >RIV/00216305:26230/13:PU106281 - isvavai.cz</a>
Alternative codes found
RIV/63839172:_____/13:10130212
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=10310" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=10310</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/FPL.2013.6645519" target="_blank" >10.1109/FPL.2013.6645519</a>

Result language
angličtina
Original language name
Memory Efficient IP Lookup in 100 Gbps Networks
Original language description
The increasing number of devices connected to the Internet together with video on demand have a direct impact to the speed of network links and performance of core routers. To achieve 100 Gbps throughput, core routers have to implement IP lookup in dedicated hardware and represent a forwarding table using a data structure, which fits into the onchip memory. Current IP lookup algorithms have high memory demands when representing IPv6 prefix sets or introduce very high pre-processing overhead. Therefore, we performed analysis of IPv4 and IPv6 prefixes in forwarding tables and propose a novel memory representation of IP prefix sets, which has very low memory demands. The proposed representation has better memory utilization in comparison to the highly optimized Shape Shifting Trie (SST) algorithm and it is also suitable for IP lookup in 100 Gbps networks, which is shown on a new pipelined hardware architecture with 170 Gbps throughput.
Czech name
—
Czech description
—

Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
23rd International Conference on Field Programmable Logic and Applications (FPL'13)
ISBN
978-1-4799-0004-6
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
1-8
Publisher name
IEEE Circuits and Systems Society
Place of publication
Porto
Event location
Porto
Event date
Sep 2, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000349452600026

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