Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106326" target="_blank" >RIV/00216305:26230/13:PU106326 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=10273" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=10273</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2013.6549798" target="_blank" >10.1109/DDECS.2013.6549798</a>

Result language
angličtina
Original language name
Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks
Original language description
With the growing speed of computer networks, core routers have to increase performance of longest prefix match (LPM) operation on IP addresses. While existing LPM algorithms are able to achieve high throughput for IPv4 addresses, the IPv6 processing speed is limited. To achieve 100 Gbps throughput, LPM operation has to be processed in dedicated hardware and a forwarding table has to fit into the on-chip memory. Current LPM algorithms need a large memory to store IPv6 forwarding tables or use compression with dynamic data structres, which can not be simply implemented in hardware. Therefore we provide analysis of available forwarding tables of core routers and propose a new representation of prefix sets. The proposed representation has very low memory demands and is suitable for high-speed pipelined processing, which is shown on new highly pipelined hardware architecture with 100 Gbps throughput.
Czech name
—
Czech description
—

Project
<a href="/en/project/ED1.1.00%2F02.0070" target="_blank" >ED1.1.00/02.0070: IT4Innovations Centre of Excellence</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
ISBN
978-1-4673-6136-1
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
108-111
Publisher name
IEEE Computer Society
Place of publication
Brno
Event location
Karlovy Vary
Event date
Apr 8, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000325168900024

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