Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106283" target="_blank" >RIV/00216305:26230/13:PU106283 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/TC.2013.78" target="_blank" >http://dx.doi.org/10.1109/TC.2013.78</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TC.2013.78" target="_blank" >10.1109/TC.2013.78</a>

Result language

angličtina

Original language name

Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing

Original language description

This paper presents an evolvable hardware system, fully contained in an FPGA, which is capable of autonomously generating digital processing circuits, implemented on an array of processing elements (PEs). Candidate circuits are generated by an embedded evolutionary algorithm and implemented by means of dynamic partial reconfiguration, enabling evaluation in the final hardware. The PE array follows a systolic approach, and PEs do not contain extra logic such as path multiplexers or unused logic, so array performance is high. Hardware evaluation in the target device and the fast reconfiguration engine used yield smaller reconfiguration than evaluation times. This means that the complete evaluation cycle is faster than software-based approaches and previous evolvable digital systems. The selected application is digital image filtering and edge detection. The evolved filters yield better quality than classic linear and nonlinear filters using mean absolute error as standard comparison metric. Results do not only show better circuit adaptation to different noise types and intensities, but also a nondegrading filtering behavior. This means they may be run iteratively to enhance filtering quality. These properties are even kept for high noise levels (40 percent). The system as a whole is a step toward fully autonomous, adaptive systems.

Czech name

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Czech description

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Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

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OECD FORD branch

20206 - Computer hardware and architecture

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2013

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

IEEE TRANSACTIONS ON COMPUTERS

ISSN

0018-9340

e-ISSN

1557-9956

Volume of the periodical

62

Issue of the periodical within the volume

8

Country of publishing house

US - UNITED STATES

Number of pages

12

Pages from-to

1481-1493

UT code for WoS article

000321221000002

EID of the result in the Scopus database

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