Hardware Architecture for the Fast Pattern Matching

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106307" target="_blank" >RIV/00216305:26230/13:PU106307 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Hardware Architecture for the Fast Pattern Matching
Original language description
As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.
Czech name
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Czech description
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Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
ISBN
978-1-4673-6133-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
120-123
Publisher name
IEEE Computer Society
Place of publication
Brno
Event location
Karlovy Vary
Event date
Apr 8, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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