Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F13%3APU106377" target="_blank" >RIV/00216305:26230/13:PU106377 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA
Original language description
This paper presents the methods of design synchronization after the partial dynamic reconfiguration of FPGA and introduces a new method inspired from previous one which is still used. The implementation of this method on TMR fault tolerant system component is described. Results of synchronization after reconfiguration process in Xilinx FPGA are presented.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2013)
ISBN
978-2-11-129175-1
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
53-56
Publisher name
Politecnico di Milano
Place of publication
Avignon
Event location
Avignon
Event date
May 30, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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