Evolutionary Design of Approximate Multipliers Under Different Error Metrics
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APU111927" target="_blank" >RIV/00216305:26230/14:PU111927 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=10513" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=10513</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2014.6868777" target="_blank" >10.1109/DDECS.2014.6868777</a>
Alternative languages
Result language
angličtina
Original language name
Evolutionary Design of Approximate Multipliers Under Different Error Metrics
Original language description
Approximate circuits are digital circuits which are intentionally designed in such a way that the specification is not met in terms of functionality in order to obtain some improvements in power consumption, performance or area, in comparison with fully functional circuits. In this paper, we propose to design approximate circuits using evolutionary design techniques. In particular, different error metrics are utilized to assess the circuit functionality. The proposed method begins with a fully functional circuit which is then intentionally degraded by Cartesian genetic programming (CGP) to obtain a circuit with a predefined error. In the second phase, CGP is used to minimize the number of gates or another error criterion. The effect of various error metrics on the search performance, area and power consumption is evaluated in the task of multiplier design.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-4799-4558-0
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
135-140
Publisher name
IEEE Computer Society
Place of publication
Warsaw
Event location
Warsaw
Event date
Apr 23, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000346734200027