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Low Latency Book Handling in FPGA for High Frequency Trading

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APU111987" target="_blank" >RIV/00216305:26230/14:PU111987 - isvavai.cz</a>

  • Result on the web

    <a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=10622" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=10622</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DDECS.2014.6868785" target="_blank" >10.1109/DDECS.2014.6868785</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Low Latency Book Handling in FPGA for High Frequency Trading

  • Original language description

    Recent growth in algorithmic trading has caused a demand for lowering the latency of systems for electronic trading. FPGA cards are widely used to reduce latency and accelerate market data processing. To create a low latency trading system, it is crucial to effectively build a  representation of the market state (book) in hardware. Thus, we have designed a new hardware architecture, which updates the book with the best bid/offer prices based on the incoming messages from the exchange. For each message a corresponding financial instrument needs to be looked up and its record needs to be updated. Proposed architecture is utilizing cuckoo hashing for the book handling, which enables low latency symbol lookup and high memory utilization. In this paper we discuss a trade-off between lookup latency and memory utilization. With average latency of 253 ns the proposed architecture is able to handle 119 275 instruments while using only 144 Mbit QDR SRAM.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2014

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

  • ISBN

    978-1-4799-4558-0

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    175-178

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Warszawa

  • Event location

    Warsaw

  • Event date

    Apr 23, 2014

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000346734200035