Automatic Construction of On-line Checking Circuits Based on Finite Automata
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APU112064" target="_blank" >RIV/00216305:26230/14:PU112064 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DSD.2014.78" target="_blank" >http://dx.doi.org/10.1109/DSD.2014.78</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2014.78" target="_blank" >10.1109/DSD.2014.78</a>
Alternative languages
Result language
angličtina
Original language name
Automatic Construction of On-line Checking Circuits Based on Finite Automata
Original language description
In this paper, the approach to the automatic development of checking circuits for unit implemented in FPGA is described. The checking circuit, also denoted as online checker, introduces fault tolerance aspects to the unit. It provides the information about correctness of the unit output. Checkers are constructed from models inferred by active automata learning which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. A platform for automatic construction of online checkers has been designed and implemented. The experimental part of the paper proves that it is possible to automatically generate the model for the online checker which describes the basic behaviour of the checked component. The obtained checker is up to six times smaller than the original component.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/LD12036" target="_blank" >LD12036: Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
17th Euromicro Conference on Digital Systems Design
ISBN
978-0-7695-5074-9
ISSN
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e-ISSN
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Number of pages
7
Pages from-to
326-332
Publisher name
IEEE Computer Society
Place of publication
Verona
Event location
Verona
Event date
Aug 27, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000358409000043