Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F14%3APU112083" target="_blank" >RIV/00216305:26230/14:PU112083 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/ICES.2014.7008716" target="_blank" >http://dx.doi.org/10.1109/ICES.2014.7008716</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ICES.2014.7008716" target="_blank" >10.1109/ICES.2014.7008716</a>

Result language

angličtina

Original language name

Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform

Original language description

The aim of this paper is to introduce a new accelerator developed to address the problem of evolutionary synthesis of digital circuits at transistor level. The proposed accelerator, based on recently introduced Xilinx Zynq platform, consists of a discrete simulator implemented in programmable logic and an evolutionary algorithm running on a tightly coupled embedded ARM processor. The discrete simulator was introduced in order to achieve a good trade-off between the precision and performance of the simulation of transistor-level circuits. The simulator is implemented using the concept of virtual reconfigurable circuit and operates on multiple logic levels which enables to evaluate the behavior of candidate transistor-level circuits at a reasonable level of detail. In this work, the concept of virtual reconfigurable circuit was extended to enable bidirectional data flow which represents the basic feature of transistor level circuits. According to the experimental evaluation, the proposed architecture speeds up the evolution in one order of magnitude compared to an optimized software implementation. The developed accelerator is utilized in the evolution of basic logic circuits having up to 5 inputs. It is shown that solutions competitive to the circuits obtained by conventional design methods can be discovered.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA14-04197S" target="_blank" >GA14-04197S: Advanced Methods for Evolutionary Design of Complex Digital Circuits</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2014

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2014 IEEE International Conference on Evolvable Systems Proceedings

ISBN

978-1-4799-4480-4

ISSN

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e-ISSN

—

Number of pages

8

Pages from-to

9-16

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Piscataway

Event location

Orlando

Event date

Dec 9, 2014

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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