Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F15%3APU116945" target="_blank" >RIV/00216305:26230/15:PU116945 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1007/978-3-319-16501-1_6" target="_blank" >http://dx.doi.org/10.1007/978-3-319-16501-1_6</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/978-3-319-16501-1_6" target="_blank" >10.1007/978-3-319-16501-1_6</a>
Alternative languages
Result language
angličtina
Original language name
Evolutionary Design of Transistor Level Digital Circuits using Discrete Simulation
Original language description
The objective of the paper is to introduce a new approach to the evolutionary design of digital circuits conducted directly at transistor level. In order to improve the time consuming evaluation of candidate solutions, a discrete event-driven simulator was introduced. The proposed simulator operates on multiple logic levels to achieve reasonable trade-off between performance and precision. A suitable level of abstraction reflecting the behavior of real MOSFET transistors is utilized to minimize the production of incorrectly working circuits. The proposed approach is evaluated in the evolution of basic logic circuits having more than 20 transistors. The goal of the evolutionary algorithm is to design a circuit having the minimal number of transistors and exhibiting the minimal delay. In addition to that, various parameter settings are investigated to increase the successrate of the evolutionary design.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/GA14-04197S" target="_blank" >GA14-04197S: Advanced Methods for Evolutionary Design of Complex Digital Circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Genetic Programming, 18th European Conference, EuroGP 2015
ISBN
978-3-319-16500-4
ISSN
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e-ISSN
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Number of pages
12
Pages from-to
66-77
Publisher name
Springer International Publishing
Place of publication
Berlin
Event location
Kodaň
Event date
Apr 8, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000361758600006