Evolutionary Design of Polymorphic Gates Using Ambipolar Transistors
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121665" target="_blank" >RIV/00216305:26230/16:PU121665 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/document/7850177/" target="_blank" >http://ieeexplore.ieee.org/document/7850177/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/SSCI.2016.7850177" target="_blank" >10.1109/SSCI.2016.7850177</a>
Alternative languages
Result language
angličtina
Original language name
Evolutionary Design of Polymorphic Gates Using Ambipolar Transistors
Original language description
The objective of the paper is to introduce a new approach to the evolutionary design of polymorphic digital circuits conducted directly at transistor level. A discrete eventdriven simulator was utilized to achieve reasonable trade-off between performance and precision. The proposed approach was evaluated on a set of polymorphic logic circuits controlled by switching the power rails. It was demonstrated that the proposed method is able to produce valid solutions. A lot of polymorphic gates based on ambipolar transistors were designed, which provide transistor savings compared to existing circuits. A new class of polymorphic gates was discovered thanks to the proposed system - gates based on conventional MOS transistors whose functions are changed by switching the power rails. They seem to have the best parameters among currently known polymorphic gates based on conventional transistors.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/LD14055" target="_blank" >LD14055: Unconventional Design Techniques for Intrinsic Reconfiguration of Digital Circuits: From Materials to Implementation</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2016 IEEE Symposium Series on Computational Intelligence
ISBN
978-1-5090-4240-1
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
1-8
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Athens
Event location
Athens
Event date
Dec 6, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—