PoLibSi: Path Towards Intrinsically Reconfigurable Components

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU134148" target="_blank" >RIV/00216305:26230/19:PU134148 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/DSD.2019.00055" target="_blank" >http://dx.doi.org/10.1109/DSD.2019.00055</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD.2019.00055" target="_blank" >10.1109/DSD.2019.00055</a>

Result language

angličtina

Original language name

PoLibSi: Path Towards Intrinsically Reconfigurable Components

Original language description

One of the main research directions of polymorphic electronics is focused on various issues connected with the design of basic polymorphic components - polymorphic gates. Without a sufficient amount of polymorphic gates offering good properties, conventional electronics will be most likely the preferred way before polymorphic electronics in application scenarios targeting multifunctional behaviour or reconfiguration. The main objective of this paper is to propose a library called PoLibSi which contains eight sets of efficient bi-functional two-input polymorphic gates, whose function is selected by mutual polarity of dedicated power rails. The gate sets differ in the transistor type (conventional MOSFET, emerging double-gate ambipolar transistors), feature the gate sets were optimized to (transistor count, delay, power consumption) and input impedance constraint. The individual gates were designed by means of using an evolutionary based approach and further validated by HSPICE simulations. Each gate implementation includes a schematic, HSPICE description and simulation results. Moreover, propagation delay and power consumption is provided for all MOSFET based gates. Furthermore, each gate set is complete - it provides efficient implementation of any pair of two-input Boolean functions. Besides providing polymorphic gates with better properties to the research society, the aim of the proposed library is to improve the synthesis of polymorphic circuits in terms of the resulting size, as it is also shown in the paper. Finally, the PoLibSi library is available at: www.fit.vutbr.cz/~inevoral/polibsi

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2019

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2019 22nd Euromicro Conference on Digital System Design (DSD)

ISBN

978-1-7281-2861-0

ISSN

—

e-ISSN

—

Number of pages

7

Pages from-to

328-334

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Kallithea, Chalkidiki

Event location

Athos Palace Hotel, Solinas, Kallithea 63077, Ch

Event date

Aug 28, 2019

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000722275400046