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Power Consumption Analysis of New Generation of Polymorphic Gates

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU135490" target="_blank" >RIV/00216305:26230/20:PU135490 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DDECS50862.2020.9095579" target="_blank" >http://dx.doi.org/10.1109/DDECS50862.2020.9095579</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DDECS50862.2020.9095579" target="_blank" >10.1109/DDECS50862.2020.9095579</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Power Consumption Analysis of New Generation of Polymorphic Gates

  • Original language description

    One of the possible ways how to accomplish multifunctional digital circuits follows the paradigm of Polymorphic electronics. Design of such circuits is closely related to the availability of suitable polymorphic gates. Unfortunately, the actual electronic properties of the polymorphic gates published in the past were way too far from matching their conventional CMOS counterparts. A new type of polymorphic gates with significantly better parameters has been recently shown: Gates whose function is determined by the polarity of dedicated supply rails. Such gates have been investigated mostly in terms of their size and propagation delay. In this paper, power consumption of exactly such gates is being analysed. That makes it possible to identify the best variants among them and subsequently compare their properties with conventional CMOS circuits. Furthermore, an extensive gate set consisting of individual polymorphic gates with the lowest power consumption was introduced together with a gate set demonstrating the best found trade-off between gate size, delay and power consumption. Both sets are integrated now into the PoLibSi library - freely available library with polymorphic gates of the new generation.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/GA19-10137S" target="_blank" >GA19-10137S: Designing and exploiting libraries of approximate circuits</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2020

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020

  • ISBN

    978-1-7281-9938-2

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

    1-6

  • Publisher name

    Institute of Electrical and Electronics Engineers

  • Place of publication

    Novi Sad

  • Event location

    Novi Sad

  • Event date

    Apr 22, 2020

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000587761500008