CMOS Gates with Second Function

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130700" target="_blank" >RIV/00216305:26230/18:PU130700 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/ISVLSI.2018.00025" target="_blank" >http://dx.doi.org/10.1109/ISVLSI.2018.00025</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ISVLSI.2018.00025" target="_blank" >10.1109/ISVLSI.2018.00025</a>

Result language
angličtina
Original language name
CMOS Gates with Second Function
Original language description
In this paper, a new approach to design of multifunctional digital circuits is presented. It is based on adoption of polymorphic electronics paradigm which permits digital circuits to exhibit more than one function while preserving the same structure. In that case only components of the circuit (gates) have to be multifunctional. Individual gates have typically built-in sensitivity to the occurrence of some phenomena invoking the function change (e.g. power supply level etc.), which means that no dedicated net is required for that purpose. One of the key advantages of such circuits is the efficiency in terms of size. In this paper, MOS transistors are exploited in an unconventional manner where the circuit function selection depends just on the condition of power supply voltage rails, which is otherwise typical for polymorphic circuits utilizing ambipolar transistors. Furthermore, a first complete set of successfully simulated two-input polymorphic gates was obtained. These gates show the best parameters of all the previously published polymorphic gates - high input impedance and low output impedance, short time of signal propagation, low power consumption and low transistor count being used. Wide range of proposed polymorphic gates (function combinations) may help to obtain more efficient results during synthesis.
Czech name
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Czech description
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Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
ISBN
978-1-5386-7099-6
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
82-87
Publisher name
IEEE Computer Society
Place of publication
Hong Kong
Event location
The Hong Kong Polytechnic University, 11 Yuk Cho
Event date
Jul 9, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000443443500015

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