FPGA Prototyping and Accelerated Verification of ASIPs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F15%3APU116997" target="_blank" >RIV/00216305:26230/15:PU116997 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/10881/" target="_blank" >https://www.fit.vut.cz/research/publication/10881/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2015.33" target="_blank" >10.1109/DDECS.2015.33</a>

Result language

angličtina

Original language name

FPGA Prototyping and Accelerated Verification of ASIPs

Original language description

In current SoC verification, the trend is to create verification solutions that are tailored to specific issues in SoC or to specific architectures. The reason is that the complexity of these systems makes it difficult to use general verification approaches such as formal or simulation-based verification. This paper presents a solution that is targeted to one particular area - Application-Specific Instruction-Set Processors (ASIP) and multi-processor systems containing several ASIPs. We propose automated FPGA prototyping and accelerated verification of these systems while the accelerated verification environment corresponds to the principles of UVM (Universal Verification Methodology) therefore can easily be integrated. Automated generation of verification environments and acceleration of verification runnning on a real hardware platform makes this solution very unique and beneficial, not only in speed, but also in debugging specific hardware issues.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2015

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems

ISBN

978-1-4799-6780-3

ISSN

—

e-ISSN

—

Number of pages

4

Pages from-to

145-148

Publisher name

IEEE Computer Society

Place of publication

Belgrade

Event location

Belgrade

Event date

Apr 22, 2015

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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