Packet Processing on FPGA SoC with DPDK
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121635" target="_blank" >RIV/00216305:26230/16:PU121635 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/document/7577395/" target="_blank" >http://ieeexplore.ieee.org/document/7577395/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/FPL.2016.7577395" target="_blank" >10.1109/FPL.2016.7577395</a>
Alternative languages
Result language
angličtina
Original language name
Packet Processing on FPGA SoC with DPDK
Original language description
One of the most important topics of today is a packet processing in data centers with respect to the power consumption and efficient utilization of computational resources. The ARM architecture has proved to be an energy efficient computational system. Together with an integrated FPGA on a single die, it offers potentially a high performance with respect to the power consumption. DPDK - a set of libraries and drivers intended primarily for fast packet processing - is becoming to be a standard approach for packet processing, especially in data centers. In this paper, we exploit the potential of packet processing based on DPDK and FPGA SoC architectures. Especially, we aim at the potential of utilizing the ARM Cortex-A9 and Cortex-A53 CPUs.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
26th International Conference on Field-Programmable Logic and Applications
ISBN
978-2-8399-1844-2
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
578-579
Publisher name
École Polytechnique Fédérale de Lausanne
Place of publication
Lausanne
Event location
Lausanne
Event date
Aug 29, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000386610400097