High Performance Computing on Low Power Devices
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121651" target="_blank" >RIV/00216305:26230/16:PU121651 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/events/pad2016/download/sbornik_pad_2016.pdf" target="_blank" >http://www.fit.vutbr.cz/events/pad2016/download/sbornik_pad_2016.pdf</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
High Performance Computing on Low Power Devices
Original language description
Nowadays, the power efficiency of modern processors is becoming more and more important next to the overall performance itself. Many programming tasks and problems do not scale very well with higher number of cores due to being memory or communication bound, therefore it is often not beneficial to use faster chips to achieve better runtimes. In this case, employing slower low power processors or accelerators may be much more efficient, mainly because it is possible to get the same results using much less energy. Dynamic runtime adjustments applied to the system based on the properties of a given algorithm, such as frequency and voltage scaling or switching off unneeded parts, may further enhance power efficiency. This paper describes the benefits of using low power chips for building an HPC cluster, the group of algorithms where this approach can be useful, possible system adjustments towards better power efficiency, results achieved so far and future plans.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Computer achitectures and diagnostics 2016
ISBN
978-80-214-5376-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
81-84
Publisher name
Faculty of Information Technology BUT
Place of publication
Brno
Event location
Bořetice
Event date
Sep 14, 2016
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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