Evolving Component Library for Approximate High Level Synthesis

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121663" target="_blank" >RIV/00216305:26230/16:PU121663 - isvavai.cz</a>

Result on the web

<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=11231" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=11231</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/SSCI.2016.7850168" target="_blank" >10.1109/SSCI.2016.7850168</a>

Result language

angličtina

Original language name

Evolving Component Library for Approximate High Level Synthesis

Original language description

An approximate computing approach has recently been introduced for high level circuit synthesis (HLS) in order to make good use of approximate circuits at system and block level. It is assumed in HLS algorithms that a component library containing various implementations of elementary circuit components is available. An open problem is how to construct such a component library in the context of approximate computing, where the component's error is a new design variable and hence many compromise implementations exist for a given component. In this paper, we first introduce a multi-objective Cartesian genetic programming method to create a comprehensive component library containing hundreds of Pareto optimal implementations of approximate 8-bit adders and multipliers, where the error, area and delay are simultaneously optimized. Another multi-objective evolutionary algorithm is employed to solve the so called binding problem of HLS, in which suitable approximate components are assigned to nodes of the data flow graph describing a complex digital circuit. Two approaches are then proposed and compared in order to reduce the size of the library of approximate components.  It is shown that a random subsampling of the component library provides satisfactory results in the context of our study. The proposed methods are evaluated using two benchmark circuits -- the reduce (sum) and DCT circuits.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2016

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2016 IEEE Symposium Series on Computational Intelligence

ISBN

978-1-5090-4240-1

ISSN

—

e-ISSN

—

Number of pages

8

Pages from-to

1-8

Publisher name

IEEE Computational Intelligence Society

Place of publication

Athens

Event location

Athens

Event date

Dec 6, 2016

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000400488302074