Relaxed equivalence checking: a new challenge in logic synthesis
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F17%3APU126402" target="_blank" >RIV/00216305:26230/17:PU126402 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11410/" target="_blank" >https://www.fit.vut.cz/research/publication/11410/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2017.7968435" target="_blank" >10.1109/DDECS.2017.7968435</a>
Alternative languages
Result language
angličtina
Original language name
Relaxed equivalence checking: a new challenge in logic synthesis
Original language description
The functional equivalence has always been the integral part of virtually every logic synthesis tool. The formal equivalence checking represents a key process that helps logic synthesis tool guarantee that two representations of a circuit design exhibit exactly the same behavior. Among others,equivalence checking is routinely applied to prove that a synthesized digital circuit is logically equivalent to the RTL source code. Although formal equivalence checking has matured greatly during the last two decades and designs with millions of gates can be handled and verified in reasonable time, a new challenge has emerged with the recent advent of approaches addressing the problem of synthesis of approximate circuits.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/GA16-17538S" target="_blank" >GA16-17538S: Relaxed equivalence checking for approximate computing</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems
ISBN
978-1-5386-0472-4
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
1-6
Publisher name
IEEE Computer Society
Place of publication
Dresden
Event location
Hotel Taschenbergpalais Kempinski, Dresden
Event date
Apr 19, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000403405200001