New Ways of Generating Large Realistic Benchmarks for Testing Synthesis Tools
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00169622" target="_blank" >RIV/68407700:21240/10:00169622 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
New Ways of Generating Large Realistic Benchmarks for Testing Synthesis Tools
Original language description
In this paper we propose several methods of generating large benchmark circuits for testing logic synthesis tools. The benchmarks are derived from real circuits, so that they are functionally equivalent to their origins. We introduce misleading and/or redundant structures into them, making the benchmark size blow up significantly, with respect to the original circuit. Such benchmarks can be advantageously used for testing logic synthesis tools; the aim is to discover whether particular synthesis processes are sensitive or immune to particular circuit transformations.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 9th International Workshop on Boolean Problems
ISBN
978-3-86012-404-8
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
Freiberg University of Mining and Technology, Institute of Computer Science
Place of publication
Freiberg
Event location
Freiberg
Event date
Sep 16, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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