Introduction to Lethal Circuit Transformations

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00235708" target="_blank" >RIV/68407700:21240/15:00235708 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1063/1.4938891" target="_blank" >http://dx.doi.org/10.1063/1.4938891</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1063/1.4938891" target="_blank" >10.1063/1.4938891</a>

Result language
angličtina
Original language name
Introduction to Lethal Circuit Transformations
Original language description
Logic optimization is a process that takes a logic circuit description (Boolean network) as an input and tries to refine it, to reduce its size and/or depth. An ideal optimization process should be able to devise an optimum implementation of a network ina reasonable time, given any circuit structure at the input. However, there are cases where it completely fails to produce even near-optimum solutions. Such cases are typically induced by non-standard circuit structure modifications. Surprisingly enough, such deviated structures are frequently present in standard benchmark sets too. We may only wonder whether it is an intention of the benchmarks creators, or just an unlucky coincidence. Even though synthesis tools should be primarily well suited for practical circuits, there is no guarantee that, e.g., a higher-level synthesis process will not generate such unlucky structures. Here we present examples of circuit transformations that lead to failure of most of state-of-the-art logic syn
Czech name
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Czech description
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Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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