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A Framework for Optimizing a Processor to Selected Application

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130711" target="_blank" >RIV/00216305:26230/18:PU130711 - isvavai.cz</a>

  • Result on the web

    <a href="https://www.fit.vut.cz/research/publication/11689/" target="_blank" >https://www.fit.vut.cz/research/publication/11689/</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/EWDTS.2018.8524733" target="_blank" >10.1109/EWDTS.2018.8524733</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    A Framework for Optimizing a Processor to Selected Application

  • Original language description

    A processor plays the main role in almost every electronics system. The use of a general purpose processor may not be profitable for a specific application, because the processor is designed for a wide set of applications. Application Specific Instruction-set Processors (ASIPs) are today applied in specific cases, where one application or a certain group of applications is performed. This paper focuses on automatic optimization of an ASIP for a given application through checking its possible configurations of key parameters (number of registers, size of caches, instruction set modification, etc.). The paper also presents designed framework which is able to optimize the given application in terms of speed, area or power consumption. The framework allows to use various optimization methods. For the processor modification, the Codasip Studio tool is used. It allows to generate all tools needed for compilation, simulation, and hardware mapping which are needed in process of ASIP design. The experiments are carried on RISC-V (Reduced Instruction Set Computing) processor described in Codasip Studio.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2018

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of IEEE East-West Design & Test Symposium

  • ISBN

    978-1-5386-5710-2

  • ISSN

  • e-ISSN

  • Number of pages

    11

  • Pages from-to

    564-574

  • Publisher name

    IEEE Computer Society

  • Place of publication

    Kazan

  • Event location

    Kazan, Rusko

  • Event date

    Sep 14, 2018

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000517795800076