Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU135655" target="_blank" >RIV/00216305:26230/19:PU135655 - isvavai.cz</a>

Result on the web

<a href="http://pesw.fit.cvut.cz/2019/PESW_2019.pdf" target="_blank" >http://pesw.fit.cvut.cz/2019/PESW_2019.pdf</a>

DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study

Original language description

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a  processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a  specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a  processor is used in multiple designs. The gal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

20206 - Computer hardware and architecture

Project

<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2019

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of the 7th Prague Embedded Systems Workshop

ISBN

978-80-01-06607-2

ISSN

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e-ISSN

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Number of pages

2

Pages from-to

20-21

Publisher name

Czech Technical University

Place of publication

Roztoky u Prahy

Event location

Roztoky u Prahy

Event date

Jun 27, 2019

Type of event by nationality

EUR - Evropská akce

UT code for WoS article

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