Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU135819" target="_blank" >RIV/00216305:26230/20:PU135819 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/12081/" target="_blank" >https://www.fit.vut.cz/research/publication/12081/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/LASCAS45839.2020.9068954" target="_blank" >10.1109/LASCAS45839.2020.9068954</a>
Alternative languages
Result language
angličtina
Original language name
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination
Original language description
A processor forms the basis of almost most of today's electronic devices. In embedded systems, the emphasis is put not only on high performance but also on the small size and low power consumption. Application-specific instruction set processors present a solution that may be optimized for specific applications by different modifications of their parameters where the trade-offs among the parameters may be represented by a Pareto frontier. In this paper, we propose a novel method of Pareto frontier merging to allow the optimization of a processor for a whole set of applications rather than a single one. We provide an experimental evaluation of the method on a model of a RISC-V processor and we show that the proposed method provides better approximation of the source Pareto frontiers than the state-of-the-art methods.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)
ISBN
978-1-7281-3427-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
1-4
Publisher name
IEEE Circuits and Systems Society
Place of publication
San José
Event location
Holiday Inn Hotel, Escazu, San José
Event date
Feb 25, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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