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From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130725" target="_blank" >RIV/00216305:26230/18:PU130725 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DSD.2018.00111" target="_blank" >http://dx.doi.org/10.1109/DSD.2018.00111</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DSD.2018.00111" target="_blank" >10.1109/DSD.2018.00111</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    From Ambipolarity to Multifunctionality: Novel Library of Polymorphic Gates Using Double-Gate FETs

  • Original language description

    Ambipolarity, a unique feature typically found in some post-silicon devices, e.g. CNT or organic FETs, is still treated today just as something rather peculiar. But in reality, it does not hinder such devices from utilization when it comes to the implementation of logic. From other point of view, this feature could be perceived as an opportunity to implement the logic in more refined and efficient way. The practical impact of ambipolarity results in devices which becomes more versatile than conventional FET element.  In this paper, a set of multifunctional logic gates based on ambipolar FETs is presented. The multifunctionality of these gates means that each gate could exhibit one of two defined functions in a given moment. The selection of their function depends on circumstances under which the circuit is operated. The proposed set of gates could be employed in multifunctional circuits using techniques and procedures established for polymorphic electronics. This field of study, yet proposed nearly 20 years ago, now offers synthesis methods and application approaches to obtain an efficient implementation of more than one function in one logic circuit.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

    <a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2018

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    2018 21st Euromicro Conference on Digital System Design

  • ISBN

    978-1-5386-7376-8

  • ISSN

  • e-ISSN

  • Number of pages

    8

  • Pages from-to

    657-664

  • Publisher name

    Institute of Electrical and Electronics Engineers

  • Place of publication

    Praha

  • Event location

    FIT ČVUT, Thákurova 9, 160 00 Praha 6

  • Event date

    Aug 29, 2018

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000537466600095