Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130755" target="_blank" >RIV/00216305:26230/18:PU130755 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11758/" target="_blank" >https://www.fit.vut.cz/research/publication/11758/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/EWDTS.2018.8524728" target="_blank" >10.1109/EWDTS.2018.8524728</a>

Result language
angličtina
Original language name
Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation
Original language description
Field Programmable Gate Arrays (FPGAs) are popular not only for their wide range of usage in embedded systems, however, they are susceptible to radiation effects. Charged particles cause the so-called Single Event Upsets (SEUs) in their configuration memory. SEUs can induce failure of the whole system. This problem is fundamental for space applications where sun radiation is more considerable than in the Earth. Two main approaches to SEU mitigation technique exist: fault masking and reparation. The most popular masking method is Triple Modular Redundancy (TMR). For the faults reparation, FPGA's capability of reconfiguration is used. It is possible to combine these approaches to obtain improved fault tolerant system. It is important to assess reliability rate of this system and, therefore, its estimation by a simulation is the main part of this paper. We propose evaluation environment which assesses the reliability of a TMR system with malfunction module reconfiguration depending on faults occurrence frequency and reconfiguration time necessary for fault reparation.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of IEEE East-West Design & Test Symposium
ISBN
978-1-5386-5710-2
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
129-134
Publisher name
IEEE Computer Society
Place of publication
Kazaň
Event location
Kazan, Rusko
Event date
Sep 14, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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