Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132059" target="_blank" >RIV/00216305:26230/19:PU132059 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11879/" target="_blank" >https://www.fit.vut.cz/research/publication/11879/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/LATW.2019.8704639" target="_blank" >10.1109/LATW.2019.8704639</a>

Result language
angličtina
Original language name
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery
Original language description
Triple Modular Redundancy (TMR) applied with various granularity combined with periodical scrubbing of a configuration memory or with run-time Partial Dynamic Reconfiguration (PDR) for fault recovery are one of the most preferred Single Event Upset (SEU) mitigation techniques used by Fault Tolerant Systems (FTS) implemented into SRAM-based FPGAs. Usage of PDR and TMR allows recovering of FTSs from all transient SEU faults and offers run-time fault mitigation compared to scrubbing methods which only correct configuration upsets and are limited by scrubbing period latency. Reconfigurable TMR architecture may require global state maintenance after PDR is applied for fault removal. In such situation, operational state of reconfigured circuit copy needs to be synchronized with remaining circuit copies which were active during PDR. This paper evaluates existing synchronization methods for reconfigurable TMR architectures and soft-core processors; presents our recent research focused on a state synchronization methodology compared to the state of the art methods and further investigates strategy for a state synchronization of TMR-protected soft-core processor neo430.
Czech name
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Czech description
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Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
20th IEEE Latin American Test Symposium (LATS 2019)
ISBN
978-1-7281-1756-0
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
32-35
Publisher name
IEEE Computer Society
Place of publication
Santiago
Event location
Hotel Fundador, Santiago de Chile
Event date
Mar 11, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000469850000036

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