Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132060" target="_blank" >RIV/00216305:26230/19:PU132060 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11905/" target="_blank" >https://www.fit.vut.cz/research/publication/11905/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2019.8724636" target="_blank" >10.1109/DDECS.2019.8724636</a>
Alternative languages
Result language
angličtina
Original language name
Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430
Original language description
Reconfigurable fault tolerant (FT) architecture can be implemented into SRAM FPGA by using combination of Partial Dynamic Reconfiguration (PDR) and Triple Modular Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which are the most common transient faults induced by cosmic radiation. SEU mitigation mechanism is required when SRAM FPGAs are integrated into safety-critical systems. An essential requirement for these systems is often to remain fail-operational and perform implemented functionality after the occurrence of a fault. In our research, we proposed a run-time FT architecture based on coarse-grained TMR with triplicated soft-core processor neo430, PDR for removing all transient SEU faults and the state synchronization allowing smooth state recovery from the inconsistent state when reconfiguration of failed processor instance was finished into the state where all three processors operate synchronously. This paper describes developed FT architecture and fault recovery strategy performing all necessary steps run-time and without additional blocking of the system functionality. The state synchronization for soft-core processor neo430 architecture is described in detail. Moreover, the paper presents developed PDR framework used for validation of proposed fault recovery strategy.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019)
ISBN
978-1-7281-0073-9
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
136-140
Publisher name
IEEE Computer Society
Place of publication
Cluj-Napoca
Event location
Cluj-Napoca
Event date
Apr 24, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000492839800003