Hash-based Pattern Matching for High Speed Networks

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU132974" target="_blank" >RIV/00216305:26230/19:PU132974 - isvavai.cz</a>

Result on the web

<a href="https://ieeexplore.ieee.org/document/8724652" target="_blank" >https://ieeexplore.ieee.org/document/8724652</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS.2019.8724652" target="_blank" >10.1109/DDECS.2019.8724652</a>

Result language

angličtina

Original language name

Hash-based Pattern Matching for High Speed Networks

Original language description

Regular expression matching is a complex task which is widely used in network security monitoring applications. With the growing speed of network links and the number of regular expressions, pattern matching architectures have to be improved to retain wire-speed processing. Multi-striding is a well-known technique to increase processing speed but it requires a lot of FPGA resources. Therefore, we focus on the design of new hardware architecture for fast pre-filtering of network traffic. The proposed pre-filter performs fast hash-based matching of short strings, which are specific for matched regular expressions. As the proposed pre-filter significantly reduces input traffic, exact pattern matching can operate on significantly lower speeds. Then the exact pattern match can be done by CPU or by a slow automaton with a few hardware resources. The paper provides analyses of false-positive detection of the pre-filter with respect to the length of matching strings. The number of false-positives is low, even if the length of the selected strings is short. Therefore input traffic can be significantly reduced. For 100 Gb links, the pre-filter reduced the input data to 1.83 Gbps using four-symbol strings.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/VI20152019001" target="_blank" >VI20152019001: Smart Application Aware Embedded Probes</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2019

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019

ISBN

978-1-7281-0073-9

ISSN

—

e-ISSN

—

Number of pages

5

Pages from-to

1-5

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Cluj-Napoca

Event location

Cluj-Napoca

Event date

Apr 24, 2019

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000492839800017