Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F21%3APU142890" target="_blank" >RIV/00216305:26230/21:PU142890 - isvavai.cz</a>

Result on the web

<a href="https://ieeexplore.ieee.org/document/9609859" target="_blank" >https://ieeexplore.ieee.org/document/9609859</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ICFPT52863.2021.9609859" target="_blank" >10.1109/ICFPT52863.2021.9609859</a>

Result language

angličtina

Original language name

Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks

Original language description

Increasing speed of network links continuously pushes up requirements on the performance of network security and monitoring systems, including their typical representative and its core function: an intrusion detection system (IDS) and pattern matching. To allow the operation of IDS applications like Snort and Suricata in networks supporting throughput of 100 Gbps or even more, a recently proposed pre-filtering architecture approximates exact pattern matching using hash-based matching of short strings that represent a given set of patterns. This architecture can scale supported throughput by adjusting the number of parallel hash functions and on-chip memory blocks utilized in the implementation of a hash table. Since each hash function can address every memory block, scaling throughput also increases the total capacity of the hash table. Nevertheless, the original architecture utilizes the available capacity of the hash table inefficiently. We therefore propose three optimization techniques that either reduce the amount of information stored in the hash table or increase its achievable occupancy. Moreover, we also design modifications of the architecture that enable resource-efficient utilization of all three optimization techniques together in synergy. Compared to the original pre-filtering architecture, combined use of the proposed optimizations in the 100 Gbps scenario increases the achievable capacity for short strings by three orders of magnitude. It also reduces the utilization of FPGA logic resources to only a third.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/VI20192022143" target="_blank" >VI20192022143: Flexible probe for lawful interceptions</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2021

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2021 International Conference on Field-Programmable Technology, ICFPT 2021

ISBN

978-1-6654-2010-5

ISSN

—

e-ISSN

—

Number of pages

9

Pages from-to

185-193

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Auckland

Event location

Auckland

Event date

Dec 6, 2021

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000792703100026