Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU135818" target="_blank" >RIV/00216305:26230/20:PU135818 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/12080/" target="_blank" >https://www.fit.vut.cz/research/publication/12080/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/LASCAS45839.2020.9068977" target="_blank" >10.1109/LASCAS45839.2020.9068977</a>

Result language
angličtina
Original language name
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks
Original language description
This research paper presents examination of the influences of faults on a control unit of smart electronic locks. A stepper motor is often used as an actuator of such smart locks and its motor controller is usually implemented in a processor. The aim of this paper is to examine the impact of faults occurring in the control processor. It should be noted that faults in such electronic systems can also be induced artificially, usually with ulterior motives. The processor can be implemented in an FPGA (Field Programmable Gate Array) in order to be able to emulate HW faults inside the processor. This allows us to use previously developed evaluation platform for fault tolerance testing. This platform allows us to monitor impact of faults both on electronic and mechanical parts of electro-mechanical system. In this paper, the evaluation of faults artificially injected in FPGA-based processor is proposed. Experiments with both single and multiple fault injections were held.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)
ISBN
978-1-7281-3427-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
1-4
Publisher name
IEEE Circuits and Systems Society
Place of publication
San José
Event location
Holiday Inn Hotel, Escazu, San José
Event date
Feb 25, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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