Hardening of Smart Electronic Lock Software against Random and Deliberate Faults

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU138618" target="_blank" >RIV/00216305:26230/20:PU138618 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/12256/" target="_blank" >https://www.fit.vut.cz/research/publication/12256/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD51259.2020.00110" target="_blank" >10.1109/DSD51259.2020.00110</a>

Result language

angličtina

Original language name

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults

Original language description

In this research paper, analysis of smart electronic lock behavior during presence of faults in its controller is examined. A typical smart electronic lock is composed of a controller unit, usually implemented in a processor, and the mechanical part, which may be for example a stepper motor. The goal of this research paper is to examine the consequences of failing controller running a partly hardened program, which we developed from the experiences we gained in our previous research. We implement the controller processor in Field Programmable Gate Array (FPGA) in order to inject faults into our components. This paper focuses on fault injection into occupied parts of Instruction Memory (IMEM) and Data Memory (DMEM). Moreover, permanent failures of the processor are simulated by fault injection into occupied Look-up Tables (LUTs) of the processor design on the FPGA. Our results show that the application of certain SW-implemented fault tolerance methods may, in opposite, degrade the hardness of the system. Our experiments imply that the IMEM is the most sensitive to fault injection, because there is no possibility for an eventual self repair. In the case of DMEM, erroneous values may be possibly repaired when the variable is rewritten back to the memory, slightly lowering the DMEM sensitivity to fault injections. The CPU itself is the least susceptible. Although faults are injected to the utilized contents only, for the CPU LUTs, a certain part of the logic may not be used to implement the required function.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2020

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings - Euromicro Conference on Digital System Design, DSD 2020

ISBN

978-1-7281-9535-3

ISSN

—

e-ISSN

—

Number of pages

4

Pages from-to

680-683

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Kranj

Event location

Portorož, Slovenia, Grand Hotel Bernardin

Event date

Aug 26, 2020

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000630443300099