FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F21%3APU139844" target="_blank" >RIV/00216305:26230/21:PU139844 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/9363276/" target="_blank" >https://ieeexplore.ieee.org/document/9363276/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TVLSI.2021.3059518" target="_blank" >10.1109/TVLSI.2021.3059518</a>
Alternative languages
Result language
angličtina
Original language name
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
Original language description
In the past few years, Capsule Networks (CapsNets) have taken the spotlight compared to traditional convolutional neural networks (CNNs) for image classification. Unlike CNNs, CapsNets have the ability to learn the spatial relationship between features of the images. However, their complexity grows because of their heterogeneous capsule structure and the dynamic routing, which is an iterative algorithm to dynamically learn the coupling coefficients of two consecutive capsule layers. This necessitates specialized hardware accelerators for CapsNets. Moreover, a high-performance and energy-efficient design of CapsNet accelerators requires exploration of different design decisions (such as the size and configuration of the processing array and the structure of the processing elements). Toward this, we make the following key contributions: 1) FEECA, a novel methodology to explore the design space of the (micro)architectural parameters of a CapsNet hardware accelerator and 2) CapsAcc, the first specialized RTL-level hardware architecture to perform CapsNets inference with high performance and high energy efficiency. Our CapsAcc achieves significant performance improvement, compared to an optimized GPU implementation, due to its efficient implementation of key activation functions, such as squash and softmax, and an efficient data reuse for the dynamic routing. The FEECA methodology employs the Non-dominated Sorting Genetic Algorithm (NSGA-II) to explore the Pareto-optimal points with respect to area, performance, and energy consumption. This requires analytical modeling of the number of clock cycles required to perform each operation of the CapsNet inference and the memory accesses to enable a fast yet accurate design space exploration. We synthesized the complete accelerator architecture in a 45-nm CMOS technology using Synopsys design tools and evaluated it for the MNIST benchmark (as done by the original CapsNet paper from Google Brain's team)
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/GA19-10137S" target="_blank" >GA19-10137S: Designing and exploiting libraries of approximate circuits</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2021
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IEEE Trans. on VLSI Systems.
ISSN
1063-8210
e-ISSN
1557-9999
Volume of the periodical
29
Issue of the periodical within the volume
4
Country of publishing house
US - UNITED STATES
Number of pages
14
Pages from-to
716-729
UT code for WoS article
000637190300011
EID of the result in the Scopus database
2-s2.0-85101800294