Reliability Analysis of the FPGA Control System with Reconfiguration Hardening

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F21%3APU142902" target="_blank" >RIV/00216305:26230/21:PU142902 - isvavai.cz</a>

Result on the web

<a href="https://www.fit.vut.cz/research/publication/12489/" target="_blank" >https://www.fit.vut.cz/research/publication/12489/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD53832.2021.00089" target="_blank" >10.1109/DSD53832.2021.00089</a>

Result language

angličtina

Original language name

Reliability Analysis of the FPGA Control System with Reconfiguration Hardening

Original language description

A computing power is important in space applications where a utilization of FPGAs is very useful. However, the FPGAs are susceptible to manifestations of radiation which can cause malfunction. Particularly dangerous are configuration memory faults known as Single Event Upsets (SEUs), which can lead to the entire system failure. Therefore, the fault-tolerant techniques are used to prevent system failures. The main motivation for the use of these techniques is to maintain the correct behavior of the system despite the occurrence of faults. In addition to fault masking, which only delay system failures due to fault accumulation, the utilization of fault mitigation by partial dynamic reconfiguration was used. Everything needed is provided by the reconfiguration controller, which is a necessary additional component of the entire system. It is also very convenient to be able to detect the occurrence of fault in the system. After that, the system does not have to be restored unnecessarily, which saves useless work of the controller. The key part is the evaluation of the resilience to faults of the system using the reconfiguration of damaged parts. In all experiments, an experimental platform was used that emulates an electromechanical system, which consists of a robot control unit on an FPGA and a simulation of their behavior on a PC. Artificial faults have been injected into this controller on the FPGA. Furthermore, reliability estimation data, which was collected from our previously published simulations, was verified on a real system in our current experimentation.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

20206 - Computer hardware and architecture

Project

<a href="/en/project/8A18014" target="_blank" >8A18014: Cyber Security for Cross Domain Reliable Dependable Automated Systems</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2021

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021

ISBN

978-1-6654-2703-6

ISSN

—

e-ISSN

—

Number of pages

4

Pages from-to

553-556

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Palermo

Event location

Palermo

Event date

Sep 1, 2021

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000728394500080