ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F22%3APU143847" target="_blank" >RIV/00216305:26230/22:PU143847 - isvavai.cz</a>

Result on the web

<a href="https://doi.org/10.1109/DDECS54261.2022.9770152" target="_blank" >https://doi.org/10.1109/DDECS54261.2022.9770152</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS54261.2022.9770152" target="_blank" >10.1109/DDECS54261.2022.9770152</a>

Result language

angličtina

Original language name

ArithsGen: Arithmetic Circuit Generator for Hardware Accelerators

Original language description

Generators of arithmetic circuits can automatically deliver various implementations of arithmetic circuits that show different tradeoffs between the key circuit parameters (delay, area, power consumption). However, existing (freely-)available generators are limited if more complex circuits with a hierarchical structure and additional architecture optimization are requested. Furthermore, they support only a few output formats. In order to overcome the above-mentioned limitations, we developed a new generator of arithmetic circuits called ArithsGen. ArithsGen can generate specific architectures of signed and unsigned adders and multipliers using basic building elements such as wires and gates.  Compared to existing generators, the user can, for example, specify the type of adders used in multipliers. The tool supports various outputs formats (Verilog, BLIF, C/C++, or integer netlists). ArithsGen was evaluated in the synthesis and optimization of generic customizable accurate and approximate adders and multipliers. Furthermore, we used the circuits generated by ArithsGen as seeds for a tool developed to automatically create approximate implementations of arithmetic circuits. We show that different initial circuits (generated by ArithsGen) significantly impact the properties of these approximate implementations. The tool is available online at https://github.com/ehw-fit/ariths-gen.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA22-02067S" target="_blank" >GA22-02067S: AppNeCo: Approximate Neurocomputing</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2022

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22)

ISBN

978-1-6654-9431-1

ISSN

—

e-ISSN

—

Number of pages

4

Pages from-to

44-47

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Prague

Event location

Prague

Event date

Apr 6, 2022

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000835725500008