Optimization of BDD-based Approximation Error Metrics Calculations

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F22%3APU144471" target="_blank" >RIV/00216305:26230/22:PU144471 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/ISVLSI54635.2022.00028" target="_blank" >http://dx.doi.org/10.1109/ISVLSI54635.2022.00028</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ISVLSI54635.2022.00028" target="_blank" >10.1109/ISVLSI54635.2022.00028</a>

Result language

angličtina

Original language name

Optimization of BDD-based Approximation Error Metrics Calculations

Original language description

Software methods introduced for automated design of approximate implementations of arithmetic circuits rely on fast and accurate evaluation of approximate candidate implementations. To accelerate the evaluation of circuit error, we propose four novel algorithms for the exact worst-case and mean absolute error analysis based on Binary Decision Diagrams. As these algorithms do not compute any absolute values in the characteristic function, which basically compares a candidate approximate circuit with a golden circuit, the error evaluation is significantly faster than the standard BDD-based error analysis. On average, the proposed algorithms are three times faster (in some cases, 30 times faster) than the baseline for 8- to 32-bit approximate adders. These results were obtained from more than 49 thousand runs with different configurations of the method. The proposed error evaluation algorithms are available as an open-source software https://github.com/ehw-fit/bdd-evaluation.

Czech name

—

Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GJ20-02328Y" target="_blank" >GJ20-02328Y: CAQtuS: Computer-Aided Quantitative Synthesis</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2022

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '22)

ISBN

978-1-6654-6605-9

ISSN

—

e-ISSN

—

Number of pages

6

Pages from-to

86-91

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Paphos

Event location

Kypr

Event date

Jul 4, 2022

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

000886230500015