Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F24%3APU151217" target="_blank" >RIV/00216305:26230/24:PU151217 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.23919/DATE58400.2024.10546795" target="_blank" >http://dx.doi.org/10.23919/DATE58400.2024.10546795</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.23919/DATE58400.2024.10546795" target="_blank" >10.23919/DATE58400.2024.10546795</a>

Result language

angličtina

Original language name

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

Original language description

A fundamental assumption for search-based circuit approximation methods is the ability to massively and efficiently traverse the search space and evaluate candidate solutions. For complex approximate circuits (adders and multipliers), common error metrics, and error analysis approaches (SAT solving, BDD analysis), we perform a detailed analysis to understand the behavior of the error analysis methods under constrained resources, such as limited execution time. In addition, we show that when evaluating the error of a candidate approximate circuit, it is highly beneficial to reuse knowledge obtained during the evaluation of previous circuit instances to reduce the total design time. When an adaptive search strategy that drives the search towards promptly verifiable approximate circuits is employed, the method can discover circuits that exhibit better trade-offs between error and desired parameters (such as area) than the same method with unconstrained verification resources and within the same overall time budget. For 16-bit and 20-bit approximate multipliers, it was possible to achieve a 75% reduction in area when compared with the baseline method.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA24-10990S" target="_blank" >GA24-10990S: Hardware-Aware Machine Learning: From Automated Design to Innovative and Explainable Solutions</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2024

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)

ISBN

979-8-3503-4859-0

ISSN

—

e-ISSN

—

Number of pages

6

Pages from-to

1-6

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Valencia

Event location

Valencia

Event date

Mar 25, 2024

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

001253778900280