Scalable Construction of Approximate Multipliers with Formally Guaranteed Worst-Case Error
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130706" target="_blank" >RIV/00216305:26230/18:PU130706 - isvavai.cz</a>
Result on the web
<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=11678" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=11678</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TVLSI.2018.2856362" target="_blank" >10.1109/TVLSI.2018.2856362</a>
Alternative languages
Result language
angličtina
Original language name
Scalable Construction of Approximate Multipliers with Formally Guaranteed Worst-Case Error
Original language description
Approximate computing exploits the fact that many applications are inherently error resilient. In order to reduce power consumption, approximate circuits such as multipliers have been employed in these applications. However, most current approximate multipliers are based on ad-hoc circuit structures and, for automated circuit approximation methods, large efficient designs are difficult to find due to the increased search space. Moreover, existing design methods do not typically provide sufficient formal guarantees in terms of error if large approximate multipliers are constructed. To address these challenges, this brief introduces a general and efficient method for constructing large high-quality approximate multipliers with respect to the objectives formulated in terms of the power-delay product and a provable error bound. This is demonstrated by means of a comparative evaluation of approximate 16-bit multipliers constructed by the proposed method and other methods in the literature.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
<a href="/en/project/GA16-17538S" target="_blank" >GA16-17538S: Relaxed equivalence checking for approximate computing</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IEEE Trans. on VLSI Systems.
ISSN
1063-8210
e-ISSN
1557-9999
Volume of the periodical
26
Issue of the periodical within the volume
11
Country of publishing house
US - UNITED STATES
Number of pages
5
Pages from-to
2572-2576
UT code for WoS article
000448911900033
EID of the result in the Scopus database
2-s2.0-85050762278