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Designing Approximate Arithmetic Circuits with Combined Error Constraints

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F22%3APU144828" target="_blank" >RIV/00216305:26230/22:PU144828 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DSD57027.2022.00110" target="_blank" >http://dx.doi.org/10.1109/DSD57027.2022.00110</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DSD57027.2022.00110" target="_blank" >10.1109/DSD57027.2022.00110</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Designing Approximate Arithmetic Circuits with Combined Error Constraints

  • Original language description

    Approximate circuits trading the power consumption for the quality of results play a key role in the development of energy-aware systems. Designing complex approximate circuits is, however, a very difficult and computationally demanding process. When deploying approximate circuits, various error metrics (e.g., mean average error, worst-case error, error rate), as well as other constraints (e.g., correct multiplication by~0), have to be considered. The state-of-the-art approximation methods typically focus on a single metric which significantly limits the  applicability of the resulting circuits. In this paper, we experimentally investigate how various error metrics and their combinations affect the reduction of the power consumption that can be achieved. To this end, we extend evolutionary-driven techniques that allow us to  effectively explore the design space of the approximate circuits. We identify principal limitations when complex error constraints are required as well as important correlations among the error metrics enabling the construction of circuits providing the best-known trade-offs between the power reduction and combined error constraints.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Result continuities

  • Project

    <a href="/en/project/GJ20-02328Y" target="_blank" >GJ20-02328Y: CAQtuS: Computer-Aided Quantitative Synthesis</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2022

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceeding of 25th Euromicro Conference on Digital System Design 2022 (DSD'22)

  • ISBN

    978-1-6654-7404-7

  • ISSN

  • e-ISSN

  • Number of pages

    8

  • Pages from-to

    785-792

  • Publisher name

    Institute of Electrical and Electronics Engineers

  • Place of publication

    Gran Canaria

  • Event location

    Maspalomas, Gran Canaria, Spain

  • Event date

    Aug 31, 2022

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article