Technology Mapping for PAIG Optimized Polymorphic Circuits

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F22%3APU147111" target="_blank" >RIV/00216305:26230/22:PU147111 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/DSD57027.2022.00112" target="_blank" >http://dx.doi.org/10.1109/DSD57027.2022.00112</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD57027.2022.00112" target="_blank" >10.1109/DSD57027.2022.00112</a>

Result language

angličtina

Original language name

Technology Mapping for PAIG Optimized Polymorphic Circuits

Original language description

The concept of polymorphic electronics allows to efficiently implement two or more functions in a single circuit, whereas the currently selected function depends on the state of the circuit operating environment. The key components of such circuits are polymorphic gates. Since the introduction of polymorphic electronics, few tens of polymorphic gates have been published. However, a large number of them exhibit parameters that fall behind ubiquitous CMOS technology. As a result of that, the perspective of their utilization for real applications becomes rather bleak. In recent years, several complete libraries of CMOS-compatible polymorphic gates were proposed. Synthesis of polymorphic circuits achieves a higher degree of complexity in comparison to the synthesis of an ordinary digital circuit. In past, many of yet proposed polymorphic circuits have been synthesized using evolutionary principles (EA, CGP, etc.). Research done in recent years indicates that the problem of scalable synthesis technique for the synthesis of complex polymorphic circuits could be solved by multi-level synthesis techniques such as And-Inverter-Graphs. The PAIG (Polymorphic And-Inverter-Graphs) concept and synthesis techniques based on it seems to be viable approach. This paper shows a how modern polymorphic gates could be used to obtain effective implementation of a real polymorphic circuit, synthesized by a PAIG based tool.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

20206 - Computer hardware and architecture

Project

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Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2022

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceeding of 25th Euromicro Conference on Digital System Design 2022 (DSD'22)

ISBN

978-1-6654-7404-7

ISSN

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e-ISSN

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Number of pages

8

Pages from-to

801-808

Publisher name

IEEE Computer Society

Place of publication

Gran Canaria

Event location

Maspalomas, Gran Canaria, Spain

Event date

Aug 31, 2022

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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