PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits Synthesis
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F19%3APU134149" target="_blank" >RIV/00216305:26230/19:PU134149 - isvavai.cz</a>
Result on the web
<a href="https://www.fit.vut.cz/research/publication/11957/" target="_blank" >https://www.fit.vut.cz/research/publication/11957/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2019.00056" target="_blank" >10.1109/DSD.2019.00056</a>
Alternative languages
Result language
angličtina
Original language name
PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits Synthesis
Original language description
Main objective of this paper is to introduce a novel methodology for scalable synthesis of multifunctional (polymorphic) digital circuits. Despite the fact that several approaches have been proposed during recent years, those are applicable for small-scale circuits only or based on various evolution-inspired techniques. Obviously, there does not exist yet scalable synthesis methodology for complex multifunctional circuits. The proposed methodology is based on And-Inverter Graphs (AIGs) with built-in extension for multifunctional circuits where the employment of rewriting technique reduces the area by sharing common resources of two different input circuits. Experiments on publicly available benchmark circuits demonstrate significant area reduction.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
22nd Euromicro Conference on Digital System Design
ISBN
978-1-7281-2861-0
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
335-342
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
Kallithea, Chalkidiki
Event location
Athos Palace Hotel, Solinas, Kallithea 63077, Ch
Event date
Aug 28, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000722275400047