Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F24%3APU151216" target="_blank" >RIV/00216305:26230/24:PU151216 - isvavai.cz</a>

Result on the web

<a href="https://arxiv.org/abs/2404.05368" target="_blank" >https://arxiv.org/abs/2404.05368</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS60919.2024.10508920" target="_blank" >10.1109/DDECS60919.2024.10508920</a>

Result language

angličtina

Original language name

Exploiting Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators

Original language description

Energy efficiency and memory footprint of a convolutional neural network (CNN) implemented on a CNN inference accelerator depend on many factors, including a weight quantization strategy (i.e., data types and bit-widths) and mapping (i.e., placement and scheduling of DNN elementary operations on hardware units of the accelerator). We show that enabling rich mixed quantization schemes during the implementation can open a previously hidden space of mappings that utilize the hardware resources more effectively. CNNs utilizing quantized weights and activations and suitable mappings can significantly improve trade-offs among the accuracy, energy, and memory requirements compared to less carefully optimized CNN implementations. To find, analyze, and exploit these mappings, we: (i) extend a general-purpose state-of-the-art mapping tool (Timeloop) to support mixed quantization, which is not currently available; (ii) propose an efficient multi-objective optimization algorithm to find the most suitable bit-widths and mapping for each DNN layer executed on the accelerator; and (iii) conduct a detailed experimental evaluation to validate the proposed method. On two CNNs (MobileNetV1 and MobileNetV2) and two accelerators (Eyeriss and Simba) we show that for a given quality metric (such as the accuracy on ImageNet), energy savings are up to 37% without any accuracy drop. 

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

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OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA24-10990S" target="_blank" >GA24-10990S: Hardware-Aware Machine Learning: From Automated Design to Innovative and Explainable Solutions</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2024

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)

ISBN

979-8-3503-5934-3

ISSN

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e-ISSN

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Number of pages

6

Pages from-to

1-6

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Kielce

Event location

Kielce

Event date

Apr 3, 2024

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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