Inference Energy Analysis in Context of Hardware-Aware NAS

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F26%3A0196475" target="_blank" >RIV/00216305:26230/26:0196475 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1109/DDECS63720.2025.11006674" target="_blank" >http://dx.doi.org/10.1109/DDECS63720.2025.11006674</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DDECS63720.2025.11006674" target="_blank" >10.1109/DDECS63720.2025.11006674</a>

Result language

angličtina

Original language name

Inference Energy Analysis in Context of Hardware-Aware NAS

Original language description

Hardware-aware neural architecture search (HW-aware NAS) methods are crucial for designing and optimizing deep neural networks (DNNs) for efficient deployment on hardware accelerators. In this work, we analyze two HW-aware NAS methods, EvoApproxNAS and ApproxDARTS, and investigate the impact of precise hardware parameters (such as energy) measurement using Timeloop on their performance. In particular, we compare this precise measurement approach with the original approach employed by EvoApproxNAS and ApproxDARTS, which relied on a simple analytical energy estimation based on the number of multiplications performed during the inference phase of the convolutional neural network (CNN). Our analysis demonstrates how the improved energy measurements enhance the search process of HW-aware NAS methods, resulting in more energy-efficient architectures. Furthermore, we highlight the importance of precise hardware parameters measurement, showing that accurate hardware modeling is critical for obtaining CNNs with good accuracy-energy trade-offs. Our results show, that without precise hardware parameter measurement, the HW-aware NAS can produce acceptable results but may fail to fully exploit the potential of hardware accelerator, especially if the 8xN-bit approximate multipliers are considered, ultimately limiting the efficiency of designed architectures.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA24-10990S" target="_blank" >GA24-10990S: Hardware-Aware Machine Learning: From Automated Design to Innovative and Explainable Solutions</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2025

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

2025 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems

ISBN

979-8-3315-2801-0

ISSN

—

e-ISSN

—

Number of pages

6

Pages from-to

161-164

Publisher name

Institute of Electrical and Electronics Engineers

Place of publication

Lyon

Event location

Lyon

Event date

May 5, 2025

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

001506891000029