Multicore design in FPGA of ZYNQ for demonstration of RPMsg Lite protocol
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26620%2F16%3APR29000" target="_blank" >RIV/00216305:26620/16:PR29000 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Multicore design in FPGA of ZYNQ for demonstration of RPMsg Lite protocol
Original language description
The design contains two MicroBlaze processors within one FPGA of ZYNQ. Both processors execute program from their own local memory, which is situated in block RAM memory (BRAM) within the FPGA part. The processors also use the common memory which is also situated in block RAM memory within FPGA part. This layout enables to demonstrate functionality of RPMsg Lite protocol. RPMsg protocol enables two heterogeneous processor cores to communicate using a shared memory. The technique uses single-writer-single-reader circular buffers to pass message buffers to the other core. This approach does not require any multicore synchronization element. The RPMsg Lite protocol is meant to be a solution for Mixed critical systems applications because of its feature to split and instantiate the system into independent blocks or subsystems. The design uses a wide FPGA flexibility of XC7Z020-1CLG484C device. All FPGA designs were synthesized in Xilinx Vivado 2016.3.
Czech name
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Czech description
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Classification
Type
G<sub>funk</sub> - Functional sample
CEP classification
BC - Theory and management systems
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Internal product ID
EMC2_FPGA_DESIGN_FOR_RPMSG_DEMON
Numerical identification
133305
Technical parameters
Konfigurace FPGA v SoC ZYNQ využívá dva soft core procesory Microblaze. RPMsg Lite komunikace probíhá mezi nimi s využitím sdílené paměti. Návrh využívá flexibilitu SoC ZYNQ XC7Z020-1CLG484C. Všechny konfigurace byly syntetizovány v prostředí Xilinx Vivado 2016.3.
Economical parameters
Demonstrace funkčnosti RPMsg Lite protokolu, jako výsledku projektu, proběhla na exitujících hardwarových prostředcích, na kterých se provádí demonstrace i jiných funkcionalit, nebylo nutné nakupovat nový hardware.
Application category by cost
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Owner IČO
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Owner name
Kybernetika pro materiálové vědy
Owner country
CZ - CZECH REPUBLIC
Usage type
A - K využití výsledku jiným subjektem je vždy nutné nabytí licence
Licence fee requirement
A - Poskytovatel licence na výsledek požaduje licenční poplatek
Web page
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